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ds07-12504-5e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89860/850 series mb89865/867/p867/w867 mb89855/857/p857/w857/t855 n description the mb89860/850 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip, microcontrollers. in addition to the f 2 mc-8l cpu core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as a timer unit, pwm timers, a uart, a serial interface, a 10-bit a/d converter, and an external interrupt. the mb89860/850 series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? various package options qfp package (80 pins): mb89860 sdip package (64 pins): mb89850 ? high-speed processing at low voltage minimum execution time: 0.4 m s/3.5 v, 0.8 m s/2.7 v (continued) n pac k ag e 80-pin plastic qfp (fpt-80p-m06) 64-pin plastic sh-dip (dip-64p-m01) 80-pin ceramic qfp (fpt-80c-a02) 64-pin plastic sh-dip (dip-64c-a06)
2 mb89860/850 series (continued) ?f 2 mc-8l family cpu core multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. ? 8-bit pwm timers: 2 channels also usable as a reload timer ?uart full-duplex double buffer synchronous and asynchronous data transfer ? 8-bit serial i/o switchable transfer direction allows communication with various equipment. ? 10-bit a/d converter conversion time: 13.2 m s activation by an external input or a timer unit capable ? external interrupt: 4 channels four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) ? bus interface functions including hold and ready functions ? timer unit outputs non-overlap three-phase waveforms to control an ac inverter motor. also usable as a pwm timer (4 channels) instruction set optimized for controllers
3 mb89860/850 series n product lineup * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) mb89865 mb89857 mb89867 mb89p857 mb89w857 mb89p867 mb89w867 classification mass production products (mask rom products) one-time prom pruducts/ eprom products, also used for evaluation rom size 16 k 8 bits (internal mask rom) note: in mb89t855, no internal rom can be used but external rom is used. 32 k 8 bits (internal mask rom) 32 k 8 bits (internal prom, programming with general- purpose eprom programmer) ram size 512 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s/10 mhz interrupt processing time: 3.6 m s/10 mhz ports input ports: 5 (all also serve as peripherals) output ports (n-ch open drain): 8 (all also serve as peripherals) i/o ports (n-ch open drain): 15 (mb89860 series only) output ports (cmos): 8 (all also serve as bus control pins) i/o ports (cmos): 32 (all also serve as bus pins or peripherals) total: 68 (53 pins for mb89850 series) timer unit 10-bit up/down count timer 1 compare registers with buffer 4 compare timer unit clear register with buffer 1 zero detection pin control 4 output channels non-overlap three-phase waveform output independent three-phase dead-time timer 8-bit pwm timer 1, 8-bit pwm timer 2 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 m s to 25.6 m s) 8-bit resolution pwm operation (conversion cycle: 102 m s to 6.528 ms) uart 8 bits clock synchronous/asynchronous data transfer capable 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 10-bit a/d converter 10-bit resolution 8 channels a/d conversion time: 13.2 m s continous activation by a compare channel 0 in timer unit or an external activation capable external interrupt 4 independent channels (edge selection, interrupt vector, source flag) rising edge/falling edge selectability. used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) standby modes sleep mode, stop mode process cmos operating voltage* 2.7 v to 6.0 v 2.7 v to 5.5 v mb89855 mb89t855 parameter part number
4 mb89860/850 series n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products 1. memory size before evaluating using the otprom (one-time prom) products (also used for evaluation), verify its differences from the product that will actually be used. take particular care on the following point: ? the stack area, etc., is set at the upper limit of the ram. 2. current consumption when operated at low speed, the product with an otprom or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. 3. mask options in the mb89p857/w857/p867/w867/t855, no option can be set. before using options check section n mask options. take particular care on the following point: ? a pull-up resistor can be set for p00 to p07, p10 to p17 and p20 to p27 only at single-chip mode. package mb89855 mb89t855 mb89857 mb89p857 mb89w857 mb89865 mb89867 mb89p867 mb89w867 dip-64p-m01 dip-64c-a06 fpt-80p-m06 fpt-80c-a02
5 mb89860/850 series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p31/so1 p30/sck1 p47/ trgi p46/z p45/y p44/x p43/rto3/w p42/ rto2/v p41/ rto1/u p40/rto0 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p64/dtti p63/int3/adst p62/int2 p61/int1 p60/int0 rst mod0 mod1 x0 x1 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc p32/si1 p33/sck2 p34/so2 p35/si2 p36/pto1 p37/pto2 v ss p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/a08 p11/a09 p12/a10 p13/a11 p14/a12 p15/a13 p16/a14 p17/a15 p20/bufc p21/hak p22/hrq p23/rdy p24/clk p25/wr p26/rd p27/ale (dip-64p-m01) (dip-64c-a06) (top view)
6 mb89860/850 series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p82 p81 p80 p76 p75 p74 p73 p72 p71 p70 mod0 mod1 x0 x1 v ss rst p27/a l e p26/rd p25/wr p24/c l k p23/rdy p22/hrq p21/hak p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 n.c. p40/rto0 p41/rto1/u p42/rto2/v p43/rto3/w p44/x v ss p45/y p46/z v cc p47/trgi p60/int0 p61/int1 p62/int2 p63/int3/adst p64/dtti p30/sck1 p31/so1 p32/si1 p33/sck2 p34/so2 p35/si2 p36/pto1 p37/pto2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p83 av ss avr av cc p57/an7 p56/an6 p55/an5 p54/an4 p53/an3 p52/an2 p51/an1 p50/an0 p84 p85 p86 p87 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 (fpt-80p-m06) (top view) (fpt-80c-a02)
7 mb89860/850 series n pin description (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-80p-m06, fpt-80c-a02 pin no. pin name circuit type function sh-dip *1 qfp *2 30 13 x0 a crystal oscillator pins (10 mhz) 31 14 x1 28 11 mod0 b operating mode selection pins connect directly to v cc or v ss . 29 12 mod1 27 16 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 56 to 49 40 to 33 p00 /ad0 to p07/ad7 d general-purpose i/o ports when an external bus is used, these ports function as multiplex pins of lower address output and data i/o. 48 to 41 32 to 25 p10 /a08 to p17/a15 d general-purpose i/o ports when an external bus is used, these ports function as upper address output. 40 24 p20/bufc f general-purpose output port when an external bus is used, this port can also be used as a buffer control output. 39 23 p21/hak f general-purpose output port when an external bus is used, this port can also be used as a hold acknowledge output. 38 22 p22/hrq d general-purpose output port when an external bus is used, this port can also be used as a hold request input. 37 21 p23/rdy d general-purpose output port when an external bus is used, this port functions as a ready input. 36 20 p24/clk f general-purpose output port when an external bus is used, this port functions as a clock output. 35 19 p25/wr f general-purpose output port when an external bus is used, this port functions as a write signal output. 34 18 p26/rd f general-purpose output port when an external bus is used, this port functions as a read signal output. 33 17 p27/ale f general-purpose output port when an external bus is used, this port functions as an address latch signal output. 2 48 p30/sck1 e general-purpose i/o port also serves as the clock i/o for the uart. this port is a hysteresis input type.
8 mb89860/850 series (continued) (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-80p-m06, fpt-80c-a02 pin no. pin name circuit type function sh-dip *1 qfp *2 1 47 p31/so1 e general-purpose i/o port also serves as the data output for the uart. this port is a hysteresis input type. 63 46 p32/si1 e general-purpose i/o port also serves as the data input for the uart. this port is a hysteresis input type. 62 45 p33/sck2 e general-purpose i/o port also serves as the clock i/o for the 8-bit serial i/o. this port is a hysteresis input type. 61 44 p34/so2 e general-purpose i/o port also serves as the data output for the 8-bit serial i/o. this port is a hysteresis input type. 60 43 p35/si2 e general-purpose i/o port also serves as the data input for the 8-bit serial i/o. this port is a hysteresis input type. 59 42 p36/pto1 e general-purpose i/o port also serves as the pulse output for the 8-bit pwm timer 1. this port is a hysteresis input type. 58 41 p37/pto2 e general-purpose i/o port also serves as the pulse output for the 8-bit pwm timer 2. this port is a hysteresis input type. 10 63 p40/rto0 e general-purpose i/o port also serves as the pulse output for the timer unit. this port is a hystereisis input type. 9, 8, 7 62, 61, 60 p41/rto1/u, p42/rto2/v, p43/rto3/w e general-purpose i/o ports also serve as the pulse output for the timer unit or a non- overlap three-phase waveform output. these ports are a hysteresis input type. 6, 5, 4 59, 57, 56 p44/x, p45/y, p46/z e general-purpose i/o ports also serve as a non-overlap three-phase output. these ports are a hysteresis input type. 3 54 p47/trgi e general-purpose i/o port also serves as the trigger input for the timer unit. this port is a hysteresis input type. 11 to 18 69 to 76 p50/an0 to p57/an7 h n-ch open-drain output ports also serve as the analog input for the a/d converter. 26 to 24 53 to 51 p60/int0 to p62/int2 i general-purpose input ports also serve as an external interrupt input. these ports are a hysteresis input type. 23 50 p63/int3/ adst i general-purpose input port also serves as an external interrupt input and as the activation trigger input for the a/d converter. this port is a hysteresis input type.
9 mb89860/850 series (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-80p-m06, fpt-80c-a02 pin no. pin name circuit type function sh-dip *1 qfp *2 22 49 p64/dtti i general-purpose input port also serves as a dead-time timer disable input. this port is a hysteresis input type. dtti input is with a noise canceller. 10 to 4 p70 to p76 g n-ch open-drain i/o ports these ports are a hysteresis input type. 3 to 1, 80, 68 to 65 p80 to p87 g n-ch open-drain i/o ports these ports are a hysteresis input type. 64 55 v cc power supply pin 32, 57 15, 58 v ss power supply (gnd) pins 19 77 av cc a/d converter power supply pin 20 78 avr a/d converter reference voltage input pin 21 79 av ss a/d converter power supply (gnd) pin use this pin at the same voltage as v ss . 64 n.c. internally connected pin be sure to leave it open.
10 mb89860/850 series n i/o circuit type (continued) type circuit remarks a ? at an oscillation feedback resitor of approximately 1 m w /5.0 v b c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input d?cmos output ?cmos input ? pull-up resistor optional (mask rom products) ? at a pull-up resistor of approximately 50 k w /5.0 v e?cmos output ? hysteresis input ? pull-up resistor optional (mask rom products) ? at a pull-up resistor of approximately 50 k w /5.0 v x1 x0 standby control signal r p-ch n-ch p-ch n-ch p-ch r p-ch n-ch p-ch r
11 mb89860/850 series (continued) type circuit remarks f?cmos output ? pull-up resistor optional (mask rom products) ? at a pull-up resistor of approximately 50 k w /5.0 v g ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional (mask rom products) ? at a pull-up resistor of approximately 50 k w /5.0 v h ? n-ch open-drain output ? analog input i ? hysteresis input ? pull-up resistor optional (mask rom products) ? at a pull-up resistor of approximately 50 k w /5.0 v p-ch n-ch p-ch r p-ch n-ch p-ch r p-ch n-ch analog input r
12 mb89860/850 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pin be sure to leave (internally connected) n.c. pin open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
13 mb89860/850 series n programming to the eprom on the mb89p867/w867/p857/w857 the mb89p867/w867/p857/w857 are an otprom version of the mb89860/850 series. 1. features ? 32-kbyte prom on chip ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in eprom mode is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p867/w867/p857/w857 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0000 h to 7fff h (note that addresses 8000 h to ffff h while operating as a single chip assign to addresses 0000 h to 7fff h in eprom mode.) (3) program to 0000 h to 7fff h with the eprom programmer. 0480 h 8000 h ffff h 0080 h 0000 h prom 32 kb not available ram i/o 0000 h 7fff h eprom 32 kb single chip eprom mode ( corresponding addresses on the eprom programmer) address
14 mb89860/850 series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. erasure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm 2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 angstroms (?)) with intensity of 12000 m w/cm 2 for 15 to 21 minutes. the internal eprom should be about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wavelengths shorter than 4000 ?. although erasure time will be much longer than with uv source at 2537 ?, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance. 7. eprom programmer socket adapter * : connect the adapter jumper pin to v ss when using. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 package compatible socket adapter dip-64p-m01 rom-64sd-28dp-8l* fpt-80p-m01 rom-80qf-28dp-8l2 program, verify aging +150?, 48 hrs. data verification assembly
15 mb89860/850 series n block diagram oscillator clock controller time-base timer external bus interface cmos output port f 2 mc-8l ram v cc , v ss 2 x0 x1 rst p00/ad0 to p07/ad7 rom 8-bit serial i/o n-ch open-drain output port p47/trgi p46/z p45/y p44/x p43/rto3/w p42/rto2/v p41/rto1/u p40/rto0 p35/si2 reset circuit (wdt) cpu cmos i/o port 8 10-bit a/d converter 8 external interrupt 8-bit pwm timer 2 p64/dtti p60/int0 to p62/int2 avr 8-bit pwm timer 1 uart timer unit (dead-time timer) n-ch open-drain i/o port port 7 and port 8 cmos i/o port input port p34/so2 p33/sck2 p32/si1 p31/so1 p30/sck1 8 8 7 8 4 3 p37/pto2 p63/int3/adst av cc av ss p80 to p87 p50/an0 to p57/an7 p70 to p76 p10/a08 to p17/a15 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc 6 mod0 mod1 * 2 : not included in the mb89850 series. p36/pto1 cmos i/o port port 6 port 4 port 3 port 2 port 0 and port 1 internal bus port 5 part number ram size rom size mb89865/855/t855* 1 mb89857/867 mb89w857/p867 512 bytes 1 kbyte 1 kbyte 16 kbytes 32 kbytes 32 kbytes (eprom) * 1 : in the mb89t855, an external rom can be used. * 2 other pins
16 mb89860/850 series n cpu core 1. memory space the microcontrollers of the mb89860/850 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89860/850 series is structured as illustrated below. memory space rom ffff h 0080 h 0000 h i/o mb89865 mb89855/t855* c000 h 0200 h rom i/o ram 512 b register ram 1 kb register 0280 h external area external area 0100 h ffff h 0080 h 0000 h 0200 h 0480 h 0100 h 8000 h mb89867/857 mb89w867/p867 mb89w857/p857 *1: the rom area is an external area depending on the mode. *2: in the mb89t855, an external rom can be used. 16 kb 32 kb 2 * 1 * 1
17 mb89860/850 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy vacancy vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr
18 mb89860/850 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
19 mb89860/850 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89860/850 series. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 register bank configuration
20 mb89860/850 series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (w) bctr external bus pin control register 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 09 h (w) wdtc watchdog timer control register 0a h (r/w) tbtc time-base timer control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (w) ddr4 port 4 data direction register 10 h (r/w) pdr5 port 5 data register 11 h vacancy 12 h (r) pdr6 port 6 data register 13 h vacancy 14 h (r/w) pdr7 port 7 data register 15 h vacancy 16 h (r/w) pdr8 port 8 data register 17 h to 1b h vacancy 1c h (r/w) ctr1 pwm control register 1 1d h (w) cmr1 pwm compare register 1 1e h (r/w) ctr2 pwm control register 2 1f h (w) cmr2 pwm compare register 2 20 h (r/w) smc uart serial mode control register 21 h (r/w) src uart serial rate control register 22 h (r/w) ssd uart serial status/data register 23 h (r/w) sidr/sodr uart serial data register 24 h (r/w) smr serial mode register 25 h (r/w) sdr serial data register
21 mb89860/850 series (continued) notes: ? do not use vacancies. ? when a read-modify-write instruction (such as bit set) is used to access a write-only register or a register containing a write-only bit, a bit designated by the instruction will have a predetermined value. however, a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. so no access to the register should be tried with any read-modefy-write instruction. address read/write register name register description 26 h (r/w) eic1 external interrupt control register 1 27 h (r/w) eic2 external interrupt control register 2 28 h (r/w) adc1 a/d converter control register 1 29 h (r/w) adc2 a/d converter control register 2 2a h (r) addh a/d converter data register (h) 2b h (r) addl a/d converter data register (l) 2c h vacancy 2d h (w) zoctr zero detection output control register 2e h (w) clrbrh compare clear buffer register (h) 2f h (w) clrbrl compare clear buffer register (l) 30 h (r/w) tcsr timer control status register 31 h (r/w) cicr compare interrupt control register 32 h (r/w) tmcr timer mode control register 33 h (r/w) coer compare/port selection register 34 h (r/w) cmcr compare buffer mode control register 35 h (r/w) dtcr dead-time timer control register 36 h (w) dtsr dead-time setting register 37 h (r/w) octbr output control buffer register 38 h (w) ocpbr0h output compare buffer register 0 (h) 39 h (w) ocpbr0l output compare buffer register 0 (l) 3a h (w) ocpbr1h output compare buffer register 1 (h) 3b h (w) ocpbr1l output compare buffer register 1 (l) 3c h (w) ocpbr2h output compare buffer register 2 (h) 3d h (w) ocpbr2l output compare buffer register 2 (l) 3e h (w) ocpbr3h output compare buffer register 3 (h) 3f h (w) ocpbr3l output compare buffer register 3 (l) 40 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
22 mb89860/850 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *: use av cc and v cc set at the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 7.0 v * a/d converter reference input voltage avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v. program voltage v pp v ss C 0.3 13.0 v mod1 pins of mb89p867/ w867 and mb89p857/w857 input voltage v i v ss C 0.3 v cc + 0.3 v output voltage v o v ss C 0.3 v ss + 0.3 v l level maximum output current i ol 20ma l level average output current i olav1 4ma p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p76, p80 to p87 i olav2 15 ma p40 to p47 l level total average output current s i olav1 30ma p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p76, p80 to p87 s i olav2 50 ma p40 to p47 h level maximum output current i oh C20ma h level average output current i ohav C4ma h level total maximum output current s i oh C20ma power consumption p d 300mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
23 mb89860/850 series 2. recommended operating conditions (av ss = v ss = 0.0 v) *: these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. note: connect the mod0 and mod1 pins to v cc or v ss . figure 1 operating voltage vs. clock operating frequency parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.7* 6.0* v normal operation assurance range* mb89867/865, mb89857/855 2.7* 5.5* v normal operation assurance range* mb89p867/w867, mb89p857/w855/t855 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v operating temperature t a C40 +85 c 1 2 3 4 5 6 1 operation assurance range operating voltage (v) clock operating frequency (mhz) 2345678910 5.5 analog accuracy assured in the v cc = av cc = 3.5 v to 6.0 v range 4.0 2.0 0.8 0.4 ( m s) minimum execution time (instruction cycle) note: the shaded area is assured only for the mb89865/867/855/857.
24 mb89860/850 series 3. dc characteristics (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p22, p23 0.7 v cc v cc + 0.3 v v ihs rst , p30 to p37, p40 to p47, p60 to p64, p70 to p76, p80 to p87 0.8 v cc v cc + 0.3 v l level input voltage v il p00 to p07, p10 to p17, p22, p23 v ss C 0.3 0.3 v cc v v ils rst , p30 to p37, p40 to p47, p60 to p64, p70 to p76, p80 to p87 v ss C 0.3 0.2 v cc v h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47 i oh = C2.0 ma 2.4 v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p76, p80 to p87 i ol = 1.8 ma 0.4 v v ol2 p40 to p47 i ol = 15 ma 1.5 v input leackage current i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p64, p70 to p76, p80 to p87, mod0, mod1 0.0 v < v i < v cc 5 m a pull-up resistance r pull rst v i = 0.0 v 25 50 100 k w with pull- up resistor power supply current i cc v cc f c = 10 mhz normal operation mode (external clock) 1518ma i ccs f c = 10 mhz sleep mode (external clock) 6 8ma i cch stop mode t a = +25 c 10 m a i a av cc f c = 10 mhz, when a/d conversion is activated 6ma input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf
25 mb89860/850 series 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : t xcyl is the oscillation cycle (1/f c ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t xcyl * ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
26 mb89860/850 series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle parameter symbol pin condition value unit remarks min. max. clock frequency f c x0, x1 110mhz clock cycle time t xcyl 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s t inst = 0.4 m s when operating at f c = 10 mhz 0.2 v cc 0.8 v cc x0 0.2 v cc 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open t xcyl p wl p wh t cf t cr x0 and x1 timing conditions clock conditions
27 mb89860/850 series (5) recommended resonator manufacturers inquiry: fujitsu limited far part number (built-in capacitor type) frequency initial deviation of far frequency (t a = +25 c) temperature characteristics of far frequency (t a = C25 c to +60 c) far-c4cb-08000-m02 8.00 mhz 0.5% 0.5% far-c4cb-10000-m02 10.00 mhz 0.5% 0.5% x0 x1 * far c1 c2 *: fujitsu acoustic resonator c1 = c2 = 20 pf 8 pf (built-in far) sample application of piezoelectric resonator (far series)
28 mb89860/850 series inquiry: kyocera corporation avx corporation north american sales headquarters: tel 1-803-448-9411 avx limited european sales headquarters: tel 44-1252-770000 avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. murata electronics north america, inc.: tel 1-404-436-1300 murata europe management gmbh: tel 49-911-66870 murata electronics singapore (pte.) ltd.: tel 65-758-4233 resonator manufacturer* resonator frequency c1 (pf) c2 (pf) r (k w ) kyocera corporation kbr-7.68mws 7.68 mhz 33 33 kbr-8.0mws 8.0 mhz 33 33 murata mfg. co., ltd. csa8.00mtz 8.0 mhz 30 30 sample application of ceramic resonator x1 * c1 c2 x0
29 mb89860/850 series (6) clock output timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. max. cycle time t cyc clk load condition: 50 pf 200 ns t xcyl 2 at 10 mhz oscillation clk - ? clk t chcl 30 100 ns approx. t cyc / 2 at 10 mhz oscillation 2.4 v 0.8 v 2.4 v clk t cyc t chcl
30 mb89860/850 series (7) bus read timing (v cc = +5.0 v 10%, f c = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value (10 mhz) unit remarks min. max. valid address ? rd time t avrl rd , a15 to a08, ad7 to ad0 load condition: 50 pf 1/4 t inst * C 64 ns ns rd pulse width t rlrh rd 1/2 t inst * C 20 ns ns valid address ? data read time t avdv ad7 to ad0, a15 to a08 1/2 t inst *nsno wait rd ? data read time t rldv rd , ad7 to ad0 1/2 t inst * C 80 ns ns no wait rd - ? data hold time t rhdx ad7 to ad0, rd 0ns rd - ? ale - time t rhlh rd , ale 1/4 t inst * C 40 ns ns rd - ? address invalid time t rhax rd , a15 to a08 1/4 t inst * C 40 ns ns rd ? clk - time t rlch rd , clk 1/4 t inst * C 60 ns ns clk ? rd - time t clrh 0ns rd ? bufc time t rlbl rd , bufc C5 ns bufc - ? valid address time t bhav a15 to a08, ad7 to ad0, bufc 5ns ale ad a rd bufc clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v t rhdx t bhav t rlbl t clrh t rhlh t avdv t rlch t rldv t rhax t rlrh t avrl
31 mb89860/850 series (8) bus write timing (v cc = +5.0 v 10%, f c = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: for information on t inst , see (4) instruction cycle. *2: these characteristics are also applicable to the bus read timing. parameter symbol pin condition value (10 mhz) unit remarks min. max. valid address ? ale time t avll ad7 to ad0, ale, a15 to a08 load condition: 50 pf 1/4 t inst *1 C 64 ns ns ale time ? address invalid time t llax 5ns valid address ? wr time t avwl wr , ale 1/4 t inst *1 C 60 ns ns wr pulse width t wlwh wr 1/2 t inst *1 C 20 ns ns write data ? wr - time t dvwh ad7 to ad0, wr 1/2 t inst *1 C 60 ns ns wr - ? address invalid time t whax wr , a15 to a08 1/4 t inst *1 C 40 ns ns wr - ? data hold time t whdx ad7 to ad0, wr 1/4 t inst *1 C 40 ns ns wr - ? ale - time t whlh wr , ale 1/4 t inst *1 C 40 ns ns wr ? clk - time t wlch wr , clk 1/4 t inst *1 C 60 ns ns clk ? wr - time t clwh 0ns ale pulse width t lhll ale t xcyl C 35 ns *2 ns ale ? clk - time t llch ale, clk t xcyl C 35 ns *2 ns ale ad a wr clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t clwh 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t llax t whlh t llch t lhll t dvwh t whdx t wlch t wlwh t whax t avwl t avll
32 mb89860/850 series (9) ready input timing (v cc = +5.0 v 10%, f c = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : these characteristics are also applicable to the read cycle. parameter symbol pin condition value unit remarks min. max. rdy valid ? clk - time t yvch rdy, clk load condition: 50 pf 60 ns * clk - ? rdy invalid time t chyx 0ns * clk ale ad a wr rdy address t yvch t chyx t yvch t chyx 2.4 v 2.4 v data 0.3 v cc 0.3 v cc 0.7 v cc 0.7 v cc note: the bus cycle is also extended in the read cycle in the same manner.
33 mb89860/850 series (10) uart and serial i/o timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck1,sck2 internal shift clock mode load condition: 50 pf 2 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 C200 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s serial clock h pulse width t shsl sck1, sck2 external shift clock mode load condition: 50 pf 1 t inst * m s serial clock l pulse width t slsh 1 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 0 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s
34 mb89860/850 series 0.8 v 2.4 v t scyc 2.4 v t slov 0.2 v cc 0.8 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc sck1 sck2 so1 so2 si1 si2 t ivsh t shix t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc t shsl 0.8 v cc 0.2 v cc 0.2 v cc sck1 sck2 so1 so2 si1 si2 internal shift clock mode external shift clock mode
35 mb89860/850 series (11) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, f c = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 trgi, dtti, adst, int0 to int3 load condition: 50 pf 2 t inst * m s peripheral input l pulse width 1 t ihil1 2 t inst * m s parameter symbol pin condition value unit remarks min. typ. max. resolution av cc = v cc 10 bit linearity error 2.0 lsb differential linearity error 1.5 lsb total error 3.0 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 av ss + 0.5 av ss + 2.5 lsb full-scale transition voltage v fst avr C 3.5 avr C 1.5 avr + 0.5 lsb interchannel disparity 4lsb a/d mode conversion time 33 t inst * m s analog port input current i ain an0 to an7 10 m a analog input voltage 0 avr v reference voltage avr 0av cc v reference voltage supply current i r avr = 5.0 v 200 m a 0.2 v cc 0.8 v cc t ihil1 0.8 v cc trgi dtti adst int0 to int3 0.2 v cc t ilih1
36 mb89860/850 series (1) a/d glossary ? resolution analog changes that are identifiable with the a/d converter ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? ?11 1111 1110) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error the total error indicates the difference between the actual value and theoretical value. this error is caused by the zero transition error, full-scale transition error, linearity error, quantization, and noise. (continued) actual conversion value 3ff 3fe 3fd 004 003 002 001 v ot 0.5 lsb av ss 1 lsb 1.5 lsb v fst avr 3ff 3fe 3fd 004 003 002 001 theoretical value av ss v nt avr (1 lsb n + 0.5 lsb) 1 lsb = 1022 (v) v nt ?(1 lsb n + 0.5 lsb) 1 lsb digital output digital output total error of digital output ??= v fst ?v ot theoretical i/o value analog input total error analog input actual conversion value
37 mb89860/850 series (continued) actual conversion value actual conversion value actual conversion value actual conversion value 004 003 002 001 av ss v ot (measured value) 3ff 3fe 3fd 3fc theoretical value avr v fst (measured value) digital output digital output zero transition error analog input full-scale transition error analog input v ot (measured value) theoretical value theoretical value actual conversion value actual conversion value actual conversion value actual conversion value digital output digital output linearity error analog input differential linearity error analog input 3ff 3fe 3fd 004 003 002 001 av ss v nt avr (1 lsb n + v ot ) 1 lsb 1 lsb v fst (measured value) n+1 n n ?1 n ?2 v (n + 1)t v nt v (n + 1)t ?v nt ?1 linearity error of digital output ??= differential linearity error of digital output ??= v nt ?(1 lsb n + v ot )
38 mb89860/850 series (2) precautions ? input impedance of the analog input pins the a/d converter used for the mb89860/850 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. anlog input pin analog channel selector sample hold circuit c = 64 pf r = 3 k w close for 15 instruction cycles after activating a/d conversion. comparator if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. . . . . analog input equivalent circuit
39 mb89860/850 series n example characteristics 1000 r pull (k w ) v cc (v) 100 10 to 1 123456 t a = +25?c r pull vs. v cc 0.0 1.0 v cc - v oh (v) v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 - 3.0 t a = +25?c v cc - v oh vs. i oh 600 500 400 300 200 100 0 i ol (ma) v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v 0 1 2 17181920 345678910111213141516 t a = +25?c v ol (mv) v cc = 6.0 v v ol vs. i ol 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) t a = +25?c v ol vs. i ol (3) h level output voltage (p00 to p07, p10 to p17, p20 to p27, p30 to p37, and p40 to p47) (4) pull-up resistance (1) l level output voltage (p00 to p07, p10 to p17, p20 to p27, p30 to p37, p50 to p57, p70 to p76, and p80 to p87) (2) l level output voltage (p40 to p47)
40 mb89860/850 series (5) h level input voltage/l level input voltage (cmos input) (6) h level input voltage/l level input voltage (hysteresis input) (7) operating supply current vs. frequency (8) operating supply current vs. v cc 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) t a = +25?c v in vs. v cc 25 20 15 10 5 0 v cc (v) f c = 10 mhz i cc (ma) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f c = 8 mhz f c = 6 mhz f c = 4 mhz t a = +25?c i cc vs. v cc 1234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) v ihs v ils t a = +25?c v in vs. v cc v ihs : v ils : threshold when input voltage in hysteresis characteristics is set to h level threshold when input voltage in hysteresis characteristics is set to l level 25 20 15 10 5 0 f c (mhz) v cc = 5.0 v v cc = 3.5 v v cc = 3.0 v 246810 t a = +25?c i cc (ma) i cc vs. f c
41 mb89860/850 series (9) sleep power supply current vs. frequency (10) sleep power supply current vs. v cc 10 8 6 4 2 0 v cc (v) f c = 10 mhz i ccs (ma) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f c = 8 mhz f c = 6 mhz f c = 4 mhz t a = +25?c i ccs vs. v cc 10 8 6 4 2 0 f c (mhz) v cc = 5.0 v v cc = 3.5 v v cc = 3.0 v 246810 t a = +25?c i ccs (ma) i ccs vs. f c
42 mb89860/850 series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
43 mb89860/850 series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
44 mb89860/850 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
45 mb89860/850 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 todf d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 ? ? c c ? a ? a
46 mb89860/850 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) +off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
47 mb89860/850 series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
48 mb89860/850 series n mask options (mb89855/857/865/867) n standard option list n ordering information option type option selection remarks power-on reset 0: without power-on reset 1: with power-on reset initial value of oscillation stabilization delay time 0: 2 18 /f c (s) (crystal oscillator) 1: 2 14 /f c (s) (ceramic oscillator) selects the initial value of the oscs bit in the stbc register during power-on reset. reset pin output 0: without reset output 1: with reset output pull-up resistor at port pin p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p64, p70 to p76, p80 to p87 1: without pull-up resistor 0: with pull-up resistor ? can be set per pin. ? p70 to p76, and p80 to p87 are used in the mb89860 series only. ? p00 to p07, p10 to p17, and p20 to p27 with a pull-up resistor can be set only for single-chip mode. mb89p857/w857/ p867/w867/t855 power-on reset available initial value of oscillation stabilization delay time 2 18 /f c (s) output at reset pin available pull-up resistor at port pin not available part number package remarks mb89865pf mb89867pf mb89p867pf 80-pin plastic qfp (fpt-80p-m06) mb89855p-sh MB89T855P-SH mb89857p-sh mb89p857p-sh 64-pin plastic sh-dip (dip-64p-m01) mb89w867cf 80-pin ceramic qfp (fpt-80c-a02) es level only mb89w857c-sh 64-pin ceramic sh-dip (dip-64c-a06) es level only parameter part number
49 mb89860/850 series n package dimensions "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 dimensions in mm (inches) 80-pin plastic qfp (fpt-80p-m06) +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c dimensions in mm (inches) 64-pin plastic sh-dip (dip-64p-m01)
50 mb89860/850 series C0.07 +0.08 0.800.10 (.0315.0040) 0.35 8.50(.335)typ 0.80(.0315) typ 22.30(.878) typ 22.00(.866) typ 1.60(.063) typ (.014.003) 0.800.10 (.0315.0040) 18.40(.725) ref (.787.010) 20.000.25 23.90(.941) typ (.006.002) 0.150.05 4.45(.175)max 0.51(.020) typ ref 12.00(.472) typ 16.31(.642) typ 16.00(.630) (.551.010) typ 17.91(.705) 14.000.25 index area 1994 fujitsu limited f80014sc-1-2 c 80-pin ceramic qfp (fpt-80p-a02) dimensions in mm (inches) +0.13 C0.08 C.003 +.005 0~9 5.84(.230)max 8.89(.350) dia typ (.134.014) 3.400.36 55.118(2.170)ref (.738.010) 18.750.25 (2.240.022) 56.900.56 (.750.010) 19.050.25 (.010.004) 0.250.05 1.270.25 (.050.010) 1.45(.057) max 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 0.46 .018 index area r1.27(.050) ref 1994 fujitsu limited d64006sc-1-2 c dimensions in mm (inches) 64-pin ceramic sh-dip (dip-64c-a06)
51 mb89860/850 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 1015, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited no. 51 bras basah road, plaza by the park, #06-04 to #06-07 singapore 189554 tel: 336-1600 fax: 336-1609 f9606 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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